Youssef Nadife

Youssef NADIFE is currently a Hardware Verification Engineer at Arteris since September 2023, where contributions include software development for automatic network-on-chip generation and exploring machine learning algorithms to improve coverage convergence in SystemVerilog (UVM) testbenches. Previously, Youssef completed an Engineering Assistant Internship at Synaptics Incorporated in June to August 2022, focusing on developing C and SystemVerilog models for simulating analog/RF blocks and establishing verification and calibration flows for model accuracy. Youssef's educational background encompasses a Master's degree in Electrical and Computer Engineering from Université du Québec à Chicoutimi (2022-Present), a Bachelor's degree in Industrial Science and Technology from ENSEIRB-MATMECA (2020-2023), and preparatory classes in Industrial Techniques and Sciences at LYCEE D'EXCELLENCE BENGUERIR (2018-2020), along with a Baccalauréat in Electrical and Technology Sciences from LYCEE QUALIFIANT ABDELLAH GUENNOUNE (2015-2018).