Yves Kondoszek

Yves Kondoszek is a seasoned Software & Hardware Verification Engineer at Arteris, with a focus on research and development for the flagship product since 2016. Expertise includes hardware design verification using Python, C++, UVM, and Verilog/SystemVerilog, in addition to software development with Python and shell scripting. Yves manages the France site IT infrastructure, overseeing multiple Linux servers and networking, while also contributing to CI deployment with tools like GitLab, Jenkins, and Docker. Prior experience includes a role as a Hardware Verification Engineer at Bull SAS from 2011 to 2016, where Yves specialized in ASIC verification and developed a block-level verification environment for a 28 nm ASIC. Yves holds a Master's degree in Electrical and Electronics Engineering from Ecole nationale supérieure de l'Electronique et de ses Applications, completed in 2011.