Pak Leung

Pak Leung is a seasoned engineering professional with extensive experience in design verification and digital design management. Currently serving as a Principal Design Verification Engineer at Astera Labs since November 2025, Pak previously held the position of Digital Design/Verification Manager at Texas Instruments, where responsibilities included defining full-chip architectures and implementing system-level test benches in SystemVerilog-UVM. Earlier in the career, notable positions included a Digital Design/DV Engineer role at Texas Instruments and a Member of Technical Staff at Creative Labs Pte Ltd, where contributions involved full-chip architecture definition, RTL development, and static timing sign-off. Additional experience encompasses project leadership at ECTIVA Inc, design engineering at OPTi Inc, and firmware maintenance at Bondwell Industrial Co. Ltd. Pak Leung holds a Master of Science degree in Electrical Engineering from Santa Clara University and a Bachelor of Engineering degree in Electrical and Electronic Engineering from The University of Hong Kong.