Shrinivas Bj

Shrinivas Bj is a Senior Verification Engineer at Astera Labs, a position held since October 2025. Previously, Shrinivas worked as a Verification Engineer at MemryX Inc. from March 2023 to October 2025, where responsibilities included leading the verification of the MX4 project and enhancing test coverage through the integration of APB, AXI3 VIPs, and custom agents. Shrinivas also has experience as an IC Design Engineer, focused on formal CSR verification and connectivity checks. Prior to this, Shrinivas was an ASIC Digital Design Engineer at Synopsys Inc., where efforts concentrated on developing FV testbenches and debugging RTL properties. Academic qualifications include a Master of Technology in VLSI Design and Embedded Systems from B. M. S. College of Engineering and a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Sir M Visvesvaraya Institute of Technology.