Tavio Guarino

Tavio Guarino is a Senior RTL Logic Designer at Astranis Space Technologies with experience in FPGA design. Tavio has also worked at IBM as an ASIC Architecture Design Intern and ASIC Verification Intern. Tavio holds a Master's degree in Computer Architecture from the University of Washington and a Bachelor's degree in Electrical and Electronics Engineering from the University of Florida. Additionally, Tavio has experience in research involving FPGA and ASIC CPU performance modeling, FPGA supercomputer thread scheduling, and heterogeneous multi-core DSP processing.