Raymond Garcia

Raymond Garcia has worked in the field of verification engineering since 2007. Theirmost recent role is Staff Verification Engineer at Axelera AI, which they have held since 2022. Prior to that, they were a Verification Specialist at IMS Nanofabrication GmbH from 2017 to 2021. From 2016 to 2017, they were a Senior Validation Engineer at Intel Corporation, where they designed verification of Intel proprietary IPs using Speman e and eVC, and was responsible for testplan updates, regression and debugging, creation of new testcases, and functional coverage creation and collection. From 2013 to 2016, they were a Staff Verification Engineer at MediaTek, where they were responsible for design verification of Ethernet Systems and sub-systems, verification of device bus of the Ethernet Chip, design of device bus reference model (UVC), Control Plane and Port System verification, and Error Case DV on SoC Level. From 2012 to 2013, they were a Senior Design Verification Engineer at Lattice Semiconductor. From 2007 to 2012, they were a Senior Design Verification Engineer at Canon Information Technologies, Philippines Inc., where they were responsible for design verification of bus bridges, interrupt controller, image decoder for network camera and printer projects, and was sent to Canon Inc. (Japan) to design a multi master-slave AXI4 SystemVerilog Wrapper and to verify a newly designed DMA controller.

Raymond Garcia attended Muntinlupa Science High School from 1998 to 2002, where they obtained a Secondary School degree. Raymond then attended Ateneo de Manila University from 2002 to 2007, where they obtained a Bachelor of Science in Electrical, Electronics and Communications Engineering.