Caio Oliveira

Caio Oliveira is an experienced engineering professional currently serving as Lead Design Engineer at Cadence Design Systems since September 2022. Previously, Caio held the position of DFT Engineer at HCL Technologies, focusing on ASIC projects related to Design for Testability. Additional roles include a Firmware Developer at FAPESP, where work centered on developing a low-cost impedance meter for biosensors, and an intern lecturer at Universidade de São Paulo, contributing to the curriculum of Applied Digital Systems. Caio has also taken on tutoring roles related to bioinformatics and laboratory automation at Universidade de Ribeirão Preto and has experience in technical support and education through various positions at LIAPE and UNAERP. Caio's early career included founding and presiding over a Computer Engineering student organization and conducting robotics research as a scholarship student at CNPq. Educational qualifications include a Master's degree in Computer Science and Computational Mathematics from ICMC - USP and a Bachelor's degree in Computer Engineering from Universidade de Ribeirão Preto.