Hao Ji

Hao Ji is a seasoned professional in the field of research and development, currently serving as Vice President of Research & Development at Cadence Design Systems since January 2003, where management of international parasitic extraction teams is a primary focus. Prior to this role, Hao Ji held the position of Product Engineer Director at Cadence, directing product engineering efforts for extraction and physical verification tools, while also establishing a global team for advanced foundry process nodes. Experience includes serving as R&D Manager and Senior Software Engineer at Celestry Design Technology, leading full-chip parasitic modeling and extraction initiatives, and as Senior Software Engineer at Ultima Interconnect Technology, specializing in interconnect resistance and capacitance extraction. Educational credentials include a Ph.D. in Computer Engineering from the University of California, Santa Cruz, and both a Master's and Bachelor's Degree in Electrical Engineering from Southeast University.