JL

Jing Liu

Senior Principal Engineer at Cadence Design Systems

Jing Liu has a background in engineering and extensive experience in the semiconductor industry, having worked at companies like Cadence, Samsung Austin R&D Center, and Texas Instruments. With a focus on DDR memory controller and PHY IP support, ARM GPU and CPU IP implementation, and design verification, Jing has a strong technical expertise in various aspects of semiconductor design. Jing also has experience as a lecturer at Shanghai Jiao Tong University and holds multiple degrees in engineering.

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Timeline

  • Senior Principal Engineer

    January, 2015 - present

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