Krunal Patel

Krunal Patel is currently working as a Principal Product Engineer at Cadence Design Systems since August 2020. Prior to this role, Krunal held positions at PerfectVIPs as a Senior Verification Engineer from November 2015 to August 2020, at GEO Semiconductor, Inc. as a Consultant - Asic Design Verification Engineer from November 2017 to October 2018, and at Sibridge Technologies as a Member of Technical Staff from November 2011 to March 2015. Krunal graduated from Nirma University in 2011 with a Bachelor of Technology (B.Tech.) in Electronics and Communications Engineering.