Kumar P.

Kumar P. is a seasoned engineering professional with a focus on application engineering and verification, currently serving as a Senior Principal Application Engineer at Cadence Design Systems since April 2018. Prior experience includes roles as a Verification Engineer at Rambus, where Kumar P. was involved in UVM verification of Ethernet protocols, and as an Engineer at Airbus, focusing on UVC design for various communication components. Kumar P. initiated a master thesis on coverage-driven verification of microprocessors for flight navigation systems, utilizing advanced algorithms and machine learning techniques. Early career experiences feature a student internship at Xaar, where hardware design for actuator monitoring was undertaken. Educational qualifications include a Master's degree in System On Chip from KTH Royal Institute of Technology and a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Global Academy Of Technology.