Mihir Shah

Mihir Shah is a Principal FPGA Design Engineer at Cadence Design Systems since February 2024, bringing extensive experience in firmware and FPGA design. Prior to this role, Mihir served as a Firmware Engineer at Varex Imaging Corporation from February 2018 to February 2024, holding positions from L2 to L4. Early in the career, Mihir gained valuable experience as an FPGA Design & Verification Intern at Signal Laboratories, Inc., and as an Electrical Engineering Intern at DEKA Research & Development. Educational qualifications include a Master's degree in Electrical and Computer Engineering from The University of Texas at Dallas and a Bachelor's degree in Mechatronics Engineering from SRM University.