Sanjay Dhar

Sanjay Dhar is a Senior Software Architect at Cadence Design Systems since July 2020, previously serving as a Principal Engineer at Synopsys from 2004 to July 2020. Sanjay possesses extensive experience in product development and deployment, particularly in FPGA-based emulation and prototyping compiler software, as well as expertise in software and algorithms for ASIC place and route optimization, clock tree synthesis, and fast circuit simulation tools. Sanjay earned a D.Sc. in Electrical Engineering from Washington University in St. Louis, having studied there from 1981 to 1987, and attended St. Xavier's College.