Satyabir Mahato

Satyabir Mahato is a highly experienced engineering professional with a focus on digital verification for SOC and IP in automotive products. Currently serving as a SR. Principal Design Engineer at Cadence Design Systems since January 2023, Satyabir previously held the position of Principal Verification Engineer at the same company. Prior experience includes working as a Member of Technical Staff at Mobiveil Inc. for AMD at their San Jose site, and as a Sr. Staff Engineer and Staff Engineer at STMicroelectronics, where Satyabir progressed quickly from Lead Engineer. Earlier roles include Senior Digital Design Engineer at LSI, focusing on digital verification for storage device SOCs, and a Project Engineer at Wipro Technologies, where initial training took place in VLSI Digital Verification Technology. Satyabir Mahato holds a Bachelor of Technology degree in Electrical and Electronics Engineering from Haldia Institute of Technology, obtained in 2009.