Cadence Design Systems
Yogesh Goel is a seasoned professional with extensive experience in product engineering and strategic customer development within the semiconductor industry. Currently serving as Corporate Vice President of the System Verification Group at Cadence Design Systems since January 2021, Yogesh previously held multiple leadership positions at Synopsys Inc from 2012 to January 2021, including Senior Vice President of Engineering. Earlier career milestones include directing teams at Cadence Design Inc and Verisity Design Systems. Notably, Yogesh contributed to the development of innovative verification and emulation technologies while at Axis Systems and Synopsys Inc. Yogesh holds an MBA in Finance and Strategy from The Wharton School, along with an MS in Computer Science from the Indian Institute of Technology, Bombay, and a BS in Computer Science from SGS Institute of Technology and Science.