Bhanushankar Gedela

Bhanushankar Gedela is a Verification Engineer at Tech Mahindra Cerium Pvt Ltd since January 2021. Prior experience includes a position as an RTL Design and Verification Trainee at Maven Silicon from May 2020 to December 2020, and a project internship at the Defence Research and Development Laboratory (DRDL) - DRDO in May 2018, focusing on the design of an FSK modulator in MATLAB and VHDL under the supervision of Scientist "E" Maneesh Kumar Devangan. Bhanushankar is currently pursuing a Master of Technology (MTech) in Microelectronics through the BITS Pilani Work Integrated Learning Programmes (2022-2024) after obtaining a Bachelor of Technology in Electronics and Communications Engineering from RGUKT Basar (2015-2019). Prior education includes PUC from Rajiv Gandhi University of Knowledge Technologies (2013-2015) and SSC from Narayana Group of Schools (2012-2013).