Mike Bly

Mike Bly is a seasoned professional in the field of computer engineering, currently serving as the Principal Datapath Architect at Ciena since January 2015, focusing on advanced development programs. Prior to this role, Mike held the position of Principal Logic Design Engineer at Ciena from 2009 to 2014, specializing in FPGA and NPU datapath architecture. Mike's extensive experience includes serving as a Staff Logic Design Engineer at World Wide Packets from March 2000 to March 2008, where custom solutions for NPU and FPGA were provided to enhance third-party chipsets, as well as system-level datapath architecture. Additionally, Mike worked as an ASIC Design Engineer at Alcatel / Packet Engines from 1996 to 2000. Mike earned a Bachelor of Science degree in Computer Engineering from the University of Idaho between 1990 and 1995.