Mehul Mistry

Mehul Mistry has a significant amount of experience in the field of engineering, specializing in ASIC and FPGA development. Mehul'smost recent position was as a Principal Design Engineer at Cirrus Logic, beginning in 2014. Prior to that, they worked as a Senior Design Engineer at Wolfson Microelectronics starting in 2012. Mehul also spent several years at ST-Ericsson, starting in 2009, where they held the position of Staff ASIC Engineer. In this role, they worked on the implementation and integration of various IPs, as well as debugging ASIC level verification tests. Mehul also has experience at ST Ericsson as an FPGA Implementation Engineer, Qinetiq as a Digital Design Engineer, Marconi as a Graduate Development Engineer, and 3com as a Student Hardware Engineer. Throughout their career, Mehul has demonstrated a strong commitment to their work and has been involved in various aspects of the design and development process.

Mehul Mistry earned a B.Eng. (Hons) in Electrical & Electronic Engineering with Professional Training from Aston University in 1999. Mehul later completed an MSc in Telecommunication Technology from Aston University in 2000. From 2004 to 2006, they pursued an MSc in Radio Frequency and Communications Engineering at the University of Bradford.