Bharath Kala Vasudevan

Bharath Kala Vasudevan is an accomplished ASIC Verification Engineer with extensive experience in the field of semiconductor verification and program development. Currently employed at Cisco since October 2021, Bharath has prior experience as a Verification Engineer at Esencia Technologies Inc. and as an ASIC Verification Engineer at Sigma Designs. Responsibilities include writing, executing, and debugging Verilog test benches, as well as evaluating results using assertions and coverage methodologies. Bharath holds a Master's degree in Electrical Engineering (VLSI) from San Jose State University and a Bachelor of Engineering in Electronics and Communication Engineering from Bangalore Institute of Technology. Additional experience includes roles as a Graduate Student Assistant at San Jose State University, a Programmer Analyst at Tata Consultancy Services, and a Global Implementation Engineer at JPMorgan Chase.