Debanjan Chatterjee

Debanjan Chatterjee has a strong background in FPGA engineering. Debanjan began their career in 2010 as an R&D Engineer at Tejas Networks, where they worked on designing, developing, and testing FPGA systems for SDH/SONET, PDH, and Carrier Ethernet Networks. Debanjan then moved on to become a Senior Engineer at Tejas Networks, where they continued this work and also developed a module for data encapsulation and extraction.

In 2013, Chatterjee joined Flextrade as a Senior Engineer. In this role, they were responsible for the end-to-end design, development, and testing of FPGA based Low Latency Exchange Market data feed adapter. Debanjan worked as an individual contributor and also took on project management and process setup responsibilities. Debanjan'sspecific contributions included developing an FPGA-based TCP+UDP stack, LZO decompression block, A/B line arbitration scheme for redundant UDP feeds, and order book building logic for Tick-by-tick market data.

Most recently, Chatterjee joined Citadel Securities in 2017 as an FPGA Engineer. Details about their specific role and responsibilities at this company are not provided.

Debanjan Chatterjee attended St. Francis De'Sales Higher Secondary School from 1991 to 2004, where they obtained their SSC degree. Debanjan then pursued their undergraduate studies at the Indian Institute of Technology, Kharagpur from 2006 to 2010, majoring in Instrumentation Engineering and receiving a B.Tech (Hons.) degree. Later, from 2015 to 2017, they attended the UC San Diego Jacobs School of Engineering, where they earned a Master of Science (M.S.) degree in Computer Engineering.