Harsha Basavaraj

Harsha Basavaraj has a diverse work experience in various companies and roles. In 2013, Harsha worked as a Project Trainee at ISRO. From 2013 to 2015, Harsha was a Software Development Engineer at Cisco, where they were involved in the development and sustenance of Cisco Unified Computing Systems Converged network adapters firmware. Harsha then joined the University of California San Diego in 2016, where they served as a Graduate Teaching Assistant for two computer architecture courses, providing assistance and grading for a large number of students. In the same year, Harsha also worked as a Research Assistant at the High Performance Computer Architecture and Compilers Group, where they explored computer design features for improving performance of Big Data, Machine Learning, and Neural Network Applications. They also implemented RTL for x86 decoders to quantify the power and area impact of Heterogenous ISAs on x86 architectures. Harsha's most recent work experience is as an FPGA Engineer at Citadel Securities, starting in 2017.

Harsha Basavaraj completed their education in a chronological sequence. Starting from the year 1995 to 2007, they attended St Mira's High School, where they obtained their S.S.L.C degree. From 2007 to 2009, they attended National PU College, Basavanagudi, and completed their Pre University education, focusing on Physics, Chemistry, Mathematics, and Biology. In 2009, Harsha enrolled in Ramaiah Institute Of Technology for their Bachelor of Engineering degree, specializing in Telecommunications Engineering, which was completed in 2013. Lastly, from 2015 to 2017, Harsha pursued a Master of Science degree in Computer Science and Engineering at UC San Diego, specializing in Computer Engineering.