Jean-sébastien Leroy

Jean Leroy has a diverse work experience in the field of engineering. Jean most recently worked at Codasip as a Principal Verification Engineer, starting in June 2023. Prior to that, they worked at Codasip as a Senior R&D Engineer from August 2020 to June 2023.

Before joining Codasip, Jean Leroy was a Staff Engineer at ARM from January 2016 to July 2020. Jean also worked at ARM from 2009 to 2015, holding various roles such as Senior Engineer, Senior Validation Engineer, and Validation Engineer. In these roles, they were responsible for multi-processor coherent memory system validation of Cortex-A17, Cortex-A12, Cortex-R7, and Cortex-A9.

Earlier in their career, Jean Leroy was an Electronic Design Engineer at INEO Défense from October 2008 to October 2009. During this time, they focused on the development of VHDL IP cores for data acquisition and signal processing, as well as a VHDL UDP/IP hardware stack.

Prior to this, Jean Leroy worked at PSI Electronics as a Verification Engineer, where they contributed to the development of a LEON-2 multiprocessor System-on-Chip. Jean also completed an internship at PSI Electronics, where they were involved in the verification of a LEON-2 System-on-Chip, developing bus functional models, verification environments, and validation IP.

Outside of their professional career, Jean Leroy had a brief period in 2020 where they took on the role of a happy dad to their daughter Lucie.

Jean Leroy obtained their MSEE degree in Electronics from Université Henri Poincaré, Nancy 1, where they studied from 2006 to 2008.