Rafael Peña Bello

Rafael Peña Bello has a diverse work experience spanning over several years. Rafael currently holds the position of Verification Lead at Codasip, where they started in March 2023. Prior to this role, Rafael worked as a Verification Engineer at the same company from July 2022 to March 2023.

Before joining Codasip, Rafael worked at Apple as a Design Verification Engineer from November 2016 to June 2022. Rafael was responsible for ensuring the accuracy and functionality of design components.

From July 2013 to October 2016, Rafael worked at Intel Corporation as a Lead Flow (Verification) Engineer.

Their previous role was as a Design Engineer at NXP (acquires Freescale Semiconductor) from February 2008 to June 2013. In this position, Rafael was involved in the development of various VIPs using System Verilog, as well as collaborating in SOC Testbench development and FPGA pre-silicon validation.

Rafael's early career included working as a Chip Designer at MAZeT from September 2005 to January 2008.

Rafael Peña Bello pursued their education in a chronological manner. From 1996 to 2001, they attended the Universidad Politécnica de Madrid, where they obtained a Master's degree in Industrial Engineering. Their field of study during this period was focused on Automation and Electronics.

Following their time at the Universidad Politécnica de Madrid, Rafael Peña Bello enrolled at the Technische Universität Darmstadt. From 2001 to 2004, they pursued a Master's degree in Electrical Engineering with a specialization in Microelectronics.

It can be inferred that Rafael Peña Bello has a solid educational background in engineering, beginning with their studies in Industrial Engineering at the Universidad Politécnica de Madrid and furthering their expertise by completing a Master's degree in Electrical Engineering at the Technische Universität Darmstadt. Their educational experiences indicate a focus on automation, electronics, and microelectronics within the field of engineering.