David Brezinski

David Brezinski has 10 years of experience in ASIC design engineering. David began their career in 2003 as an Intern at Unisys, where they wrote verification tests in TCL. In 2004, they joined Vitesse Semiconductor as an ASIC Design Engineer, where they wrote random and directed tests for a SAS Expander, as well as made fixes and enhancements to the original design. In 2006, they moved to Marvell as a Senior ASIC Design Engineer, where they conducted static timing analysis throughout design of ASIC, guided the layout team to design floorplan and guide layout tool throughout the project, and closed timing at the end of the project over multiple modes and temperature/process corners. In 2011, David joined Seagate Technology as a Staff Engineer in SOC Development. Lastly, in 2022, they joined Cornelis Networks as a Senior ASIC Design Engineer.

David Brezinski obtained a Bachelors of Electrical Engineering degree from the University of Minnesota between 1999 and 2003, with a field of study in Electrical Engineering.