Jan Snoeijs

Jan Snoeijs is currently a PhD student at CSEM and ETH Zürich since September 2024. Prior to this role, Jan Snoeijs worked at Riverlane from October 2020 to September 2024, holding positions as Senior FPGA and Embedded Systems Designer and FPGA and Embedded Systems Designer, contributing to the development of software for quantum computing. Jan Snoeijs has experience as an Engineering Consultant at GO Concept and completed a Master's thesis at EPFL focused on SoC-FPGA implementation of recurrent neural networks for biomedical applications. Additional experience includes an internship at Atracsys LLC in high-speed IR-camera tracking and an internship at CERN in the data preserving group. Jan Snoeijs earned a Master of Science in Electrical and Electronic Engineering from EPFL in 2019 and a Bachelor in Electrical Engineering from the same institution in 2017, preceded by a high school diploma (French Baccalauréat) in Sciences.