Ramprasad R.

Ramprasad R. has worked in the hardware engineering field since 2004. Ramprasad began their career at Wipro Technologies as a Senior Design Engineer and Module Lead, where they were responsible for IEEE 1394 Link Layer IP, AES Encryption IP for Audio-Video Streams, and JTAG TAP controller verification. From 2006 to 2008, Ramprasad worked at Conexant as a Senior Design Engineer, where they were responsible for Scan/ATPG circuit implementation in 90nm and 65nm SOCs with and without EDT Compression for multiple set-top box and broadband SOCs. From 2008 to 2013, Ramprasad worked at LSI R&D India Pvt Ltd. as an IC Design Engineer, where they were responsible for 36/48 port SAS2/SAS3 Expander SOCs and RAID Accelerator Engine at 40nm and 28nm technology nodes. From 2013 to 2018, Ramprasad worked at Broadcom Limited as an IC Design Engineer, where they were responsible for x16/x8/x4/x2 PCIe IP Core, 36/48 port SAS2/SAS3 Expander SOCs and RAID Accelerator Engine at 40nm, 28nm and 16FF technology nodes. From 2018 to 2022, Ramprasad worked at Google as a Hardware Engineer, where they were responsible for Interchip communication design for TPU chips and key blocks in Titan M security chip - ICache, IO Pinmux, Voltage/Freq Spike detector & LDO auto calibration. Ramprasad is currently employed as an ASIC Design Engineer at d-Matrix. Ramprasad also completed their MS in EE at the University of Colorado Colorado Springs in 2014, where they designed and implemented embedded hardware for K-Means clustering algorithm, built System Verilog based test bench for MIPS processor, and designed hardware for Brick and Paddle game.

Ramprasad R. attended the University of Colorado Colorado Springs from 2014 to 2016 and earned a Master of Science (M.S.) in Electrical and Electronics Engineering. Prior to that, they attended the University of Mumbai from 2000 to 2004, where they obtained a BE in Electronics. Before that, they attended Saraswati Vidyalaya High School.