Jules Mauffret

Soc Verification Engineer at ELSYS Design

Jules Mauffret has a diverse work experience in the field of electronics and engineering. Jules started their career as a Stagiaire at BARILLEC SAS in 2015, where they gained valuable experience. In 2016, Jules joined éolane as a Stagiaire R&D communications sans fil before being promoted to Ingénieur en électronique numérique. In 2017, they transitioned to Elsys Design as an FPGA Engineer and later became a SoC Verification Engineer.

Jules Mauffret pursued their education from 2011 to 2016 at ENIB, where they obtained a Master's degree in Electrical, Electronic, and Communication Engineering.

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