Mohammed Yassine Kaabouch

Mohammed Yassine Kaabouch is currently working as an ASIC Verification Engineer at Elsys Design since October 2019. In this role, they are responsible for defining the architecture of the test bench and developing a verification environment, including scoreboard, coverage, assertions, sequences, and tests.

Prior to that, Mohammed worked as an intern at SATT Sud-Est from April 2019 to October 2019. During this internship, they focused on modeling a Soc architecture using SystemC TLM and testing the internally developed PwClkARCH library for power consumption evaluation and power management strategies.

From November 2018 to March 2019, Mohammed undertook two projects at Faculté des Sciences et Technologies. Mohammed Yassine also completed a final year project from April 2018 to June 2018.

Earlier in their career, Mohammed gained industry experience as an intern at LafargeHolcim in 2017, where they worked on designing a remote communication system using microcontrollers and RX/TX communication modules.

Additionally, they completed internships at GREIF FLEXIBLE in 2015 and CEAC in 2013.

Mohammed Yassine Kaabouch pursued their education in the field of electrical, electronic, and industrial computer engineering. From 2017 to 2019, they attended Université de Lorraine, where they obtained a Master's degree. Prior to that, from 2016 to 2017, they studied Electronic and Optic for Embedded Systems at Faculté des sciences et techniques Limoges. Additionally, between 2012 and 2014, they completed their BTS (Brevet de Technicien Supérieur) in Electronic Systems at an undisclosed institution.