Bharani Rajendiran

Bharani Rajendiran has a diverse work experience in the field of ASIC design engineering. Bharani is currently working as a Sr ASIC design engineer at Esperanto Technologies, Inc since July 2023. Prior to this, they worked at Aeva, Inc as a Sr ASIC Design Engineer from May 2021 to July 2023.

Before their role at Aeva, Inc, Bharani was employed at Micron Technology as a Digital Design Engineer from September 2018 to May 2021. Bharani also worked at Qualcomm as a Digital Design Engineer from August 2013 to September 2018, and at Cirrus Logic as a Digital Design Engineer from March 2010 to August 2013.

Bharani's work experience also includes positions at Intel as a Design Engineer from May 2008 to May 2009, where they were responsible for developing emulation and simulation friendly models for RAM, and at Wipro Technologies as a Project Engineer from July 2005 to July 2007, where they worked on the development and customization of WLAN IP implementing IEEE 802.11 a/b/g standard for customers.

Bharani Rajendiran has a Bachelor's degree in Electronics and Communication Engineering from the National Institute of Technology, Tiruchirappalli. Additionally, they hold a Master of Science degree in Electrical Engineering with a specialization in VLSI from Arizona State University. Prior to their higher education, Bharani attended S. R. V. Higher Secondary School in Rasipuram. Further details regarding the start and end years for each educational experience are not provided.