Krishna Chaitanya Vemula

Krishna Chaitanya Vemula is a seasoned ASIC Design Engineer with a strong background in functional verification, currently employed at Synopsys Inc since January 2022. Key responsibilities include working on the RISC-V core's execution unit and FPU, along with executing trace functionalities. Previously, Krishna held the position of ASIC Design Engineer I, focusing on design verification and functional debugging using automation scripts and GUI testing. Early career experience includes a graduate technical internship involving design verification of ARC-HS and a program analyst trainee role at Cognizant. Educational qualifications include a Bachelor of Technology in Electrical and Electronics Engineering from Lovely Professional University and high school education in sciences from Sri Chaitanya Junior College, complemented by training in ARM7TDMI at C-DAC, Mohali.