Shih-Hong Jheng

Shih-Hong Jheng is a Senior IC Design Engineer with experience in Delay Lock Loop (DLL) circuit design and Built-in self-test (BIST) application on DDR1/2/3/4, LPDDR2/3, and MRAM circuit design. They have previously worked at 鈺創科技, 珠海南北極, and Nanya Technology, with a background in both production engineering and analog IC design. Shih-Hong Jheng holds a Master's degree in Electrical Engineering from Chang Gung University.