Chia-An Hsu

Chia-An Hsu has extensive experience in design verification and engineering, beginning with a role as a Second Lieutenant and Company Chief Counselor in the ROC Army, where leadership skills were developed while managing a company of up to 180 personnel. Chia-An Hsu later interned at SMIC, contributing to the development of silicon proven cells and supporting analog IP design projects. Subsequently, Chia-An Hsu served as a Verification IP Engineer at Avery Design Systems, focusing on protocol compliance testing for Ethernet and CAN systems. From May 2019 to April 2021, Chia-An Hsu worked at MediaTek as a Design Verification Engineer, verifying WiFi 6 IP and enhancing test cases and verification components. Currently, Chia-An Hsu is an ASIC Design Verification Engineer at Google, contributing to advanced verification projects in the semiconductor industry. Academic qualifications include a Bachelor of Science from National Chi Nan University, postgraduate study at National Cheng Kung University, and a Master of Engineering from Peking University in Integrated Circuits.