Chen-Yong Cher

Dr. Chen-Yong Cher is the CTO, Infrastructure at Graphen, focusing on the design and development of the production software back-end and infrastructure.

He received his B.S., M.S. and Ph.D. in Electrical and Computer Engineering from Purdue University. He subsequently joined IBM Research Center for 13 years, where he worked on performance, thermal, process variation, power and soft error reliability for ASIC and server-class microprocessors. He was the principal performance, power and soft error reliability architect for Power Edge-of-Network (EN) and BlueGene/Q compute chips, of which the latter is the main compute engine for the Lawrence Livermore National Lab’s Sequoia supercomputer that became the fastest supercomputer in the world (TOP500) in November 2012. He has been an IEEE senior member since 2013. He is a co-author of ~25 patents and ~40 technical papers. He was an IBM Master Inventor and received several corporate awards. He has received three best paper awards, and is a recipent of the 2014 Mahboob Khan Outstanding Industry Liaison/Associate Award.

Some of his past projects include thermal-aware scheduling in the Linux kernel to reduce power, machine learning of supercomputer event logging and failure event prediction (published in SC2014); hardware thread priority scheduling in a power5 SMT to improve latency (ISCA2008), enable memory garbage collection in Cell SPE accelerators (VEE2010), and he co-invented a pre-fetching technique for DFS traversal in Java Virtual Machine memory management (ASPLOS2004). Most recently through collaborating with Stanford University and University of British Columbia, he also published techniques to protect systems and GPUs from cosmic rays.