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Vasilis Tsitsis

Junior Verification Engineer at HDL Design House

Vasilis Tsitsis is currently working as a Junior verification engineer at HDL Design House since January 2023. Prior to this, Vasilis was employed as an IT Support Technician at Germanos from June 2021 to January 2023. Vasilis holds a Bachelor's degree in Computer Science and Engineering from the Technological Educational Institute of Thessaly.

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Timeline

  • Junior Verification Engineer

    January, 2023 - present

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