Satish Srerambatla

Satish Srerambatla is a seasoned CPU RTL Design Engineer with extensive experience in the semiconductor industry. Currently serving as a CPU RTL Design Engineer Staff at I Machines, Inc., Satish is focused on developing RISC-V based CPU cores and managing the Out of Order portion of the CPU. Previous roles include serving as a Staff Engineer at Ventana Micro Systems and a CPU RTL Design Engineer at Intel Corporation, where responsibilities involved micro-architecture and RTL design for advanced CPU units. Prior experience includes roles at Qualcomm as an ASIC Design Engineer, contributing to L3 cache design, and an ASIC Design Intern, where Satish supported performance metrics in caching systems. Early career experience at Sony India Software Centre included work in firmware development for Sony Bravia TVs. Satish holds a Master's degree in VLSI and Micro architecture from North Carolina State University and a Bachelor's degree in Electrical, Electronics, and Communications Engineering from the National Institute of Technology Warangal.