Ayushi Agarwal

Ayushi Agarwal is currently a Sr. Project Scientist and PhD student at the Indian Institute of Technology in Delhi, involved in the Memory and Embedded Architecture Research Group led by Prof. Preeti Ranjan Panda. Prior experience includes serving as a Research Scholar at the SRC Research Scholars Program, focusing on cache hierarchy management in Multiprocessor System on Chips (MPSoCs), and a Technical Intern at NXP Semiconductors in the Performance Architecture Group. Ayushi's background also includes roles as a Project Engineer at IIT Delhi, Research Engineer at the National University of Singapore specializing in deep learning architecture, and various positions at Qualcomm, including Design Engineer and Interim Intern, where contributions were made to system-on-chip frontend design and validation processes. Ayushi holds a Bachelor's degree in Electronics and Communications Engineering from MNNIT, Allahabad, and is pursuing a PhD in Computer Science at IIT Delhi.