Walter Budziak

Walter Budziak is a Senior Analog Design Engineer at Intrinsix Corp. since August 2014, specializing in analog IC design within CMOS 55nm technology and top-level behavioral modeling of energy harvesting architectures using Cadence, Verilog-A, and Maple. Prior to this, Walter served as an Analog Designer for Power Management at Texas Instruments from August 2007 to August 2014, where development of DC-DC buck converter architectures occurred, alongside system level and transistor level design using Cadence-Spectre tools in CMOS 65nm technology. Walter began the career as a Design Engineer at Integrated Circuit Designs from June 2000 to August 2007, collaborating with customers on DC-DC boost converter architectures and conducting system-level design and simulation using Spice tools. Walter holds a BSET in Electrical Engineering from the Rochester Institute of Technology, earned between 1987 and 1992.