Erik Schneider

Erik Schneider is an experienced FPGA Design Engineer currently working at Jabil since July 2022, previously holding the position of FPGA Design Engineer at the same company. Prior to this role, Erik Schneider gained valuable experience as an Information Technology Engineering Intern at Jaros, Baum & Bolles from August 2020 to May 2022, and as a Systems Test and Integration Intern at G3 Technologies, Inc. from August 2019 to January 2020. Erik Schneider's early career also includes an IT Intern position at Hunter Douglas, Inc. from January 2019 to May 2019. Erik Schneider earned a Bachelor of Engineering degree in Computer Engineering from Stevens Institute of Technology, completed in 2022.