Kaushik Khambhadiya

Kaushik Khambhadiya is an accomplished FPGA Design Engineer currently employed at JMA Wireless since May 2022, focusing on RTL development for 5G ORAN-based radios and FPGA design implementation. Prior experience includes a role as an FPGA Design Intern, where hardware was developed for 5G NR mmWave Small cell radio and Wireless O-RAN radios. Earlier, Khambhadiya worked as a Digital Design Engineer Intern at JK Electrical, contributing to the design of an on-chip control unit for a multi-phase servo voltage stabilizer and developing digital logic using Verilog and VHDL. Academic qualifications include a Master of Science in Electrical Engineering from The University of Texas at Dallas, a Bachelor of Engineering in Electronics and Communications Engineering from Government Engineering College Bhavnagar, and ongoing studies in Digital Signal Processing at UC San Diego Extended Studies.