Romain TUSZEWSKI

Romain Tuszewski has extensive work experience in hardware design and engineering. Romain is currently working as a Senior Hardware Design Engineer at Kalray, where their responsibilities include architecture, specification, and design. Romain'sexpertise lies in Soc, PCIe, HW Cache, and DDR.

Prior to joining Kalray, Romain worked at PLDA for a significant period of time. Romain served as a Design Manager from 2015 to 2019, where they led design projects and managed teams. Before that, they held various roles at PLDA, including Product Leader and Project Leader, where their responsibilities included architecture definition, RTL design of IP for Asic and FPGA, and non-recurring engineering for strategic customers. Romain also worked as an Asic/FPGA Designer at PLDA, where they focused on RTL development and hardware validation of PCI-Express controllers dedicated to FPGA.

Before joining PLDA, Romain worked at Bull Amesys Conseil as an FPGA Designer and R&D Electronic Engineer. During their time there, they worked as a consultant for Thales Avionics, where they were responsible for the validation and maintenance of an acquisition and digital processing module embedded in ballistic trajectory calculation equipment.

Romain's earliest work experience was at Thales Air Systems, where they worked as an R&D Electronic Engineer.

Overall, Romain Tuszewski has demonstrated a strong background in hardware design, architecture, and engineering throughout their career.

Romain Tuszewski started their education journey in 1993 at Lycée Thérèse d'Avila. Romain completed their secondary education there in 1996, however, no specific degree or field of study is mentioned.

In 1996, Romain moved on to attend Faidherbe. The duration of their studies at this institution spanned until 1998. Although no degree is specified, it can be presumed that they pursued studies in MP et PSI*.

Finally, from 1998 to 2001, Romain studied at Grenoble INP - UGA, where they obtained an Engineer's degree in Microelectronics.