Gopal Iyer

Gopal Iyer is a seasoned professional in the semiconductor industry, currently serving as Senior Director of Silicon Development at Lattice Semiconductor since May 2024. Previously, Iyer held the role of Engineering Leader at Intel Corporation from October 2011 to November 2024, where significant contributions included delivering four generations of memory solutions that generated over $5 billion in lifetime revenue and leading the productization of SoC subsystems on 10nm Agilex FPGAs, contributing an additional $2 billion in revenue. Prior experience includes serving as Senior Design Engineering Manager at Altera, focusing on advanced memory subsystems, and as a Senior Design Engineer at Link A Media Devices, specializing in defect detection features for Read Channel SoCs. Academic credentials include a Master of Science in Electrical Engineering from Georgia Institute of Technology and a Bachelor of Engineering in Electronics and Telecommunication from Savitribai Phule Pune University.