Siew Ling Yeoh

Siew Ling Yeoh is the Vice President of Engineering at Lattice Semiconductor with previous experience at Intel Corporation and Altera. Siew Ling has a strong background in managing global silicon development teams, driving engineering efficiency improvements, and overseeing digital design and verification teams. With a Bachelor's Degree in Computer System Engineering from RMIT University, Siew Ling has a proven track record of leadership and technical expertise in the semiconductor industry.