Varun Krishna Kayala

Varun Krishna Kayala is currently a Product and Test Engineer at Lattice Semiconductor, where responsibilities include post-silicon tasks related to defining guard bands on ATE, bench correlations, and PVT characterization, alongside automating testing and report generation for IC/Wafer level validation. Prior experience includes a role as a Senior Product Engineer at Intel Corporation, contributing to the enablement of four next-generation client computing products and ensuring system marginality validation. Varun also held the position of Product Development Engineer at Intel, focusing on developing methodologies for circuit marginality validation, executing stress tests, and automating validation processes. Varun holds a Master of Science in Electrical and Electronics Engineering from Portland State University and a Bachelor of Technology in Electronics and Communications Engineering from Kakatiya University.