Deekshitha R is a Senior SOC Verification Engineer at L&T Semiconductor Technologies, building on experience as a Senior Design Verification Engineer at Qualcomm and a Verification Engineer at SmartDV Technologies India Private Limited. They possess expertise in Universal Verification Methodology (UVM), SystemVerilog, and Application-Specific Integrated Circuits (ASIC), among other skills. Deekshitha holds a Bachelor of Engineering degree in Electronics and Communication Engineering from St. Joseph Engineering College, where they studied from 2013 to 2017.
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