LUBIS EDA
Dr. Tobias Ludwig is the Chief Executive Officer of LUBIS EDA, a position held since August 2021, where a long-held dream of establishing a company has been realized. Prior to this, Dr. Ludwig served as the Business Development Manager for EXIST-FT and as a Doctoral Researcher at RPTU Kaiserslautern-Landau from 2012 until April 2022, specializing in Electronic Design Automation. Additional experience includes roles as a Research Assistant focused on software development and embedded systems verification, as well as serving as a Teaching Assistant at Michigan State University in 2014. Dr. Ludwig holds a Ph.D. in Electronic Design Automation from RPTU Kaiserslautern-Landau, obtained in 2021, and a Diplom in Informationstechnik from the same institution, completed in 2015.
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LUBIS EDA
LUBIS EDA is helping customers to find simulation-resistant and corner-case bugs in high-risk silicon design or IP blocks. Our formal verification service enables you to: 1) Reach your silicon design verification goals faster 2) Uncover hard to find functional bugs in your design 3) Require less RTL simulation time 4) Stay within your budget and tape-out schedule 5) Avoid re-spins and improve designer productivity We functionally verify your RTL with formal techniques and iteratively communicate bugs we find. You get short feedback cycles, reduce your time spent on RTL verification and higher-quality designs. What makes us special? We work with an innovative formal verification methodology, resulting in an easy to use, high quality formal Verification IP. Instead of writing SVA properties by hand we established a property generation flow. During a verification service project, we build a propriatary model that enables us to generate VIP. The VIP can later be used in simulation and/or formal verification of your choice.