Jason Yereb

Jason Yereb is an experienced ASIC Physical Design Engineer currently working at Marvell Technology since July 2022, focusing on top-level and block-level Physical Design down to 3 nm. Prior to Marvell, Yereb spent nearly a decade at Cyient, where responsibilities included top-level physical design for a 12 nm ASIC in collaboration with IBM Research, and contributing to multiple tapeouts in 14 nm technology, notably achieving the first customer design for the GlobalFoundries ASIC Design Center. Yereb's career began at IBM, where engagement as a Physical Design Engineer lasted from June 1996 to July 2013. Educational qualifications include a Bachelor of Science in Electrical Engineering from Clarkson University.