Fazila Naz

Fazila Naz is a skilled Design Verification Engineer with extensive experience in developing UVM-based testbenches and standalone verification, particularly in RISC-V core components and Advanced Encryption Standard implementations. Currently employed at MaxLinear since February 2023, Fazila previously worked as a contractor at Analog Devices India and gained valuable SOC/IP level verification experience at NXP Semiconductors. Additional expertise includes proficiency in Verilog, SystemVerilog, and UVM, complemented by a Bachelor of Engineering in Electronics and Communications from Mangalore Institute of Engineering and Technology, completed in 2018.