Valentine Bordais

Valentine Bordais is an engineer with a focus on digital design and FPGA implementation. Currently working at Elsys Design since April 2023 as a Stage Ingénieur FPGA, Valentine is responsible for developing intellectual property (IP) such as GPIO and UART for communication with an AXILITE bus, alongside conducting unit tests to ensure component functionality. Previously, Valentine gained experience as a Stagiaire en conception numérique at 3D PLUS, where the study of Xilinx Soft Error Mitigation (SEM) IP was undertaken. At CNES, Valentine served as a Stagiaire, verifying electronic equipment for photo sensors to ensure compliance with specifications. Valentine holds an engineering degree from ESIEE Paris and has completed a DUT in Mesures Physiques at Université Paris Cité, following a scientific Baccalauréat at Lycée Michel Anguier.