Valerie Vaz

Valerie Vaz has held various roles in the engineering industry since 2016. Valerie began their career as an Intern at Kallows Engineering India Pvt. Ltd. in 2016. In 2017, they held the role of Trainee at Citrix and Senior Layout Engineer I, Mask Design Engineer, and Technical Lead at Sankalp Semiconductor. Currently, they are an Analog Layout Engineer at Nanusens since 2022.

Valerie Vaz completed their Bachelor of Engineering in Electrical, Electronics and Communications Engineering from DON BOSCO COLLEGE OF ENGINEERING, FATORDA, MARGAO in 2017. In November 2022, they obtained a certification in ESD Layout from IC Mask Design.