Jonathan Turenne

Jonathan Turenne is an experienced hardware engineer currently employed at Nokia since February 2016, where responsibilities include supporting and maintaining critical processes for a major SOC project. Prior to Nokia, Jonathan worked at AMD as a MTS ASIC/Layout Design Engineer from April 2012 to February 2016 and served as a Principal Technical Analyst at Staples from June 2009 to April 2012, focusing on IT tools integration. Earlier experience includes roles as a Software Engineer at Powerwave Cognition and a Senior Hardware Engineer at Alcatel-Lucent. Jonathan holds a Bachelor of Science in Computer Engineering from SUNY Polytechnic Institute and a Bachelor of Science in Computer Science from Utica University.